Some embodiments of the present invention are generally related to processor busses, and more particularly to detecting when more than one line in a bus is asserted.
In many microprocessor environments, busses may be used to connect various components as a mean of transferring signals and other data. One type of bus typically includes a collection of wires or lines that normally assert only one line or wire at a time. Busses are prone to various error conditions, which cause incorrect results. Error detection can be critical to processor stability and overall performance. Of the many types of errors that may occur, one of the more serious is when more than one line or wire asserts or goes hot at the same time. For example, when a soft error occurs, more than one line is asserted, causing errors in the processing of computer instructions.
Previous solutions to this problem include using extensive logic to examine every wire in a bus in relation to every other wire in the bus. This method is inefficient and expensive when the number of wires (N) is large, because the number of the (N−1)! states to monitor.
The invention is now described with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is generally indicated by the left-most digit(s) in the corresponding reference number.